The relentless pursuit of miniaturized semiconductor devices continues to challenge the limitations of conventional semiconductor materials and fabrication techniques. Conventional semiconductor devices typically comprise a plurality of active devices in or on a common semiconductor substrate, e.g., CMOS devices comprising at least a pair of PMOS and NMOS transistors in spaced adjacency. Current technology utilizes crystalline semiconductor wafers as substrates, such as a lightly p-doped epitaxial (“epi”) layer of silicon (Si) grown on a heavily-doped, crystalline Si Substrate. The low resistance of the heavily-doped substrate is necessary for minimizing susceptibility to latch-up, whereas the light doping of the epi layer permits independent tailoring of the doping profiles of both the p-type and n-type wells formed therein as part of the fabrication sequence, thereby resulting in optimal PMOS and NMOS transistor performance.
The use of the very thin epi layers, i.e., several μm thick, is made possible by utilizing shallow trench isolation (“STI”), which advantageously minimizes up-diffusion of p-type dopant(s) from the more heavily-doped substrate into the lightly-doped epi layer. In addition, STI allows for closer spacing of adjacent active areas by avoiding the “bird's beak” formed at the edge of each LOCOS isolation structure. STI also provides better isolation by creating a more abrupt structure, reduces the vertical step from active area to isolation to improve gate lithography control, eliminates the high temperature field oxidation step that can cause problems with large diameter, i.e., 8 inch, wafers, and is scalable to future logic technology generations.
Conventional practices include forming a semiconductor layer, such as silicon (Si) or silicon-germanium (Si—Ge), on an insulating substrate, or over an insulation layer formed on a substrate. Such technology sometimes is referred to as Silicon-on-Insulator (SOI) technology. Silicon-on-Insulator metal oxide silicon (MOS) technologies have a number of advantages over bulk silicon MOS transistors. These advantages include: reduced source/drain capacitance and hence improved speed performance at higher-operating frequencies; reduced N+ to P+ spacing and hence higher packing density due to ease of isolation; and higher “soft error” upset immunity (i.e., the immunity to the effects of alpha particle strikes).
Silicon-on-Insulator technology is characterized by the formation of a thin silicon layer for formation of the active devices over an insulating layer, such as an oxide, which is in turn formed over a substrate. Transistor sources and drains are formed by, for example, implantations into the silicon layer while transistor gates are formed by forming a patterned oxide and conductor (e.g., metal) layer structure. Such structures provide a significant gain in performance by having lower parasitic capacitance (due to the insulator layer) and increased drain current due to floating body charging effects (since no connection is made to the channel region and charging of the floating body provides access towards a majority of carriers which dynamically lower the threshold voltage, resulting in increased drain current). However, the floating body can introduce dynamic instabilities in the operation of such a transistor.
Conventional SOI field effect transistor's (FET's) have floating bodies in which the body or channel region of the FET is located on an insulator and not electrically connected to a fixed potential. These devices are known as partially depleted SOI devices and have the aforementioned advantages and disadvantages. Fully depleted SOI devices are those in which the layer of semiconductor is sufficiently thin, such that the entire thickness of the body regions is depleted of majority carriers when in the off state and both diffusions are at ground. Fully depleted devices offer additional advantages, such as reduced short channel effect, increased transconductance and reduced threshold voltage sensitivity to changes in body doping. Furthermore, the kink effects and threshold voltage shifts caused by body charging in partially depleted devices are reduced. The fully depleted devices do not have a neutral region in the channel and thus do not allow for charging and discharging of the body corresponding to the change in threshold voltage. Additionally, the fully depleted devices do not show hysterisis effect.
Semiconductor devices typically contain various different types of transistors, e.g., N-channel MOS, P-channel MOS, low Vt and high Vt transistors, as well as wide and narrow transistors. In order to optimize the operating speed of an integrated circuit it would be advantageous to provide efficient methodology enabling the fabrication of various types of transistors having a tunable channel thickness which can be precisely controlled or tailored for a particular implementation. It would also be advantageous to provide methodology enabling the fabrication of a semiconductor device based on an SOI substrate with both partially depleted and fully depleted transistors, consistent with the desired characteristics of the particular device for a particular implementation.
Accordingly, a need exists for efficient methodology enabling the fabrication of various types of semiconductor devices comprising transistors having tunable channel thicknesses. There exists a particular need for methodology enabling the fabrication of semiconductor devices based on SOI substrates with both partially depleted and fully depleted transistors, depending upon the desired characteristics of the device for a particular implementation.